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wedpz512k72s-xbx 1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 fast clock speed: 150, 133, and 100mhz fast access times: 3.8ns, 4.2ns, and 5.0ns fast oe# access times: 3.8ns, 4.2ns, and 5.0ns high performance 3-1-1-1 access rate 2.5v 5% power supply common data inputs and data outputs byte write enable and global write control six chip enables for depth expansion and address pipeline internally self-timed write cycle burst control pin (interleaved or linear burst sequence) automatic power-down for portable applications commercial, industrial and military temperature ranges packaging: ? 152 pbga package 17 x 23mm 512k x 72 synchronous pipeline burst zbl sram features description benefits 30% space savings compared to equivalent tqfp solution reduced part count 24% i/o reduction laminate interposer for optimum tce match low pro le reduce layer count for board routing suitable for hi-reliability applications user con gurable as 1m x 36 or 2m x 18 upgradable to 1m x 72 (contact factory for availability) the wedc syncburst - sram employs high-speed, low-power cmos design that is fabricated using an advanced cmos process. wedc?s 32mb syncburst srams integrate two 512k x 36 ssrams into a single bga package to provide 512k x 72 con guration. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (clk). the zbl or zero bus latency memory utilizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied ?high or low.? asynchronous inputs include the sleep mode enable (zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing exibility for incoming signals. * this product is under development, is not quali ed or characterized and is subject to change without notice.
wedpz512k72s-xbx 2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 functional block diagram a0-18 bw a # bw b # bw c # bw d # we 0 # oe 0 # clk 0 # cke 0 # cs 10 # cs 20 # cs 20 adv 0 lb 0 # zz sa bw a # bw b # bw c # bw d # we 0 # oe 0 # clk cke# cs 1 # cs 2 # cs 2 adv lb 0 # zz dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqpd dqd 0-7 dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqpd dqd 0-7 512k x 36 ssram bw e # bw f # bw g # bw h # we 1 # oe 1 # clk 1 # cke 1 # cs 113 # cs 21 # cs 21 # adv 1 sa bw a # bw b # bw c # bw d # we 0 # oe 0 # clk cke cs 1 # cs 2 # cs 2 adv lb 0 # zz 512k x 36 ssram dqpa dqa 0-7 dqpb dqb 0-7 dqpc dqc 0-7 dqph dqd 0-7 dqpe dqe 0-7 dqpf dqf 0-7 dqpg dqg 0-7 dqph dqh 0-7
wedpz512k72s-xbx 3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 pin configuration (top view) notes: dnu means do not use and are reserved for future use. * pin f8 reserved for a19 upgrade to 1m x 72. 123456789 a - adv0 oe 0 # dqb 2 dqb 4 dqb 6 dnu dqa 6 dqa 2 b cke 0 #we 0 # dqb 7 dqb 5 dqb 3 dqb 0 dqa 7 dqa 3 dqa 1 c clk 0 cs 20 # dqc 2 dqpc dqpb dqb 1 dqd 7 dqa 4 dqa 0 d bwa# bwb# dqc 3 v ss v ss v ss dqd 6 dqa 5 dqpa e bwc# bwd# dqc 4 v ccq v ccq v ccq dqd 5 dqpd zz fcs 10 #cs 20 dqc 5 v ccq v ccq v ss dqd 4 dnu* a 0 ga 7 dqc 0 dqc 7 v ss v cc v cc dqd 3 a 1 a 3 ha 18 dqc 1 dqc 6 v cc v cc v cc dqd 2 a 2 a 5 ja 9 a 6 dqf 2 v ss v ss v ss dqd 1 a 4 a 16 ka 8 dqf 4 dqf 3 v cc v cc v cc dqd 0 a 14 a 15 la 17 dqf 5 dqf 6 v cc v cc v ss dqe 6 a 12 a 13 m adv 1 oe 1 # dqf 7 v ss v ccq v ssq dqe 7 a 10 a 11 n cke 1 #we 1 # dqpf v ccq v ccq v ccq dqe 5 dqe 3 lbo# p clk 1 cs 21 # dqf 1 v ss v ss v ss dqe 4 dqe 2 dqe 0 r bwe# bwf# dqf 0 dqg 1 dqg 4 dqh 1 dqh 2 dqe 1 dqpe t bwg# bwh# dqg 0 dqg 2 dqg 5 dqh 0 dqh 4 dqh 7 dqph ucs 11 #cs 21 dqg 3 dqpg dqg 6 dqg 7 dqh 3 dqh 5 dqh 6
wedpz512k72s-xbx 4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 burst sequence table note: lbo pin must be tied to high or low, and floating state must not be allowed. (interleaved burst, lbo# = high) lbo# pin high case 1 case 2 case 3 case 4 a1 a0 a1 a0 a1 a0 a1 a0 first address fourth address 00011011 01001110 10110001 11100100 (linear burst, lbo# = low) lbo# pin high case 1 case 2 case 3 case 4 a1 a0 a1 a0 a1 a0 a1 a0 first address fourth address 00011011 01101100 10110001 11000110 the wedpz512k72s-xbx is an zbl ssram designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe#, lbo# and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally generated by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable (cke#) pin allows the operation of the chip to be suspended as long as necessary. when cke# is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. nbl ssram latches external address and initiates a cycle when cke and adv are driven low at the rising edge of the clock. output enable (oe#) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke# is driven low, the write enable input signals we# are driven high, and adv driven low. the internal array is read between the rst rising edge and the second rising edge of the clock and the data is latched in the output register. at the second clock edge the data is driven out of the sram. during read operation oe# must be driven low for the device to drive out the requested data. function description write operation occurs when we# is driven low at the rising edge of the clock. bw#[h:a] can be used for byte write operation. the pipe-lined zbl ssram uses a late- late write cycle to utilize 100% of the bandwidth. at the rst rising edge of the clock, we# and address are registered, and the data associated with that address is required two cycles later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo# pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after two cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates after two cycles of wake up time.
wedpz512k72s-xbx 5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 truth tables synchronous truth table write truth table we# bw#a bw#b bw#c bw#d operation hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllllw rite all bytes lhhhhw rite abort/nop ce#x adv we# bw#x oe# cke# clk address accessed operation h lxxxl n/a deselect xhxxxl n/a continue deselect llhxll external address begin burst read cycle xhxxll next address continue burst read cycle llhxhl external address nop/dummy read xhxxhl next address dummy read llllxl external address begin burst write cycle xhxlxl next address continue burst write cycle lllhxl n/a nop/write abort xhxhxl next address write abort xxxxxh current address ignore clock notes: 1) x means ?don?t care.? 2) the rising edge of clock is symbolized by ( ). 3) a continue deselect cycle can only be entered if a deselect cycle is executed rst. 4) write# = l means write operation in write truth table. write# = h means read operation in write truth table. 5) operation nally depends on status of asynchronous input pins (zz and oe#). 6) ce#x refers to the combination of cs#1 and cs#2. notes: 1) x means ?don?t care.? 2) all inputs in this table must meet setup and hold time around the rising edge of clk ( ). 3) replace bw#a with bw#e, bw#b, with bw#f, bw#c with bw#g and bw#d with bw#h for operation of ic2.
wedpz512k72s-xbx 6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 description symbol conditions 150mhz (max) 133mhz (max) 100mhz (max) units notes power supply current: operating i dd device selected; all inputs v il or v ih ; cycle time t cyc min; v cc = max; output open 700 650 600 ma 1 power supply current: standby i sb2 device deselected; v cc = max; all inputs v il or v ih all inputs static; clk frequency = max output open, zz v cc - 0.2v 120 120 120 ma clock running standby current i sb device deselected; v cc = max; all inputs v ss + 0.2 or v cc - 0.2; f = max ; zz v il 180 180 160 ma absolut maximum ratings* v in voltage or any other pin relative to v ss -0.3v to +3.6v voltage on v cc supply relative to v ss -0.3v to +3.6v storage temperature (bga) -55c to +150c electrical characteristics (-55c t a +125c) * stress greater than those listed under ?absolute maximum ratings: may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci cation is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability. description symbol conditions min max units notes input high (logic 1) voltage v ih 1.7 v cc +0.3 v 1 input low (logic 0) voltage v il -0.3 0.7 v 1 input leakage current i il v cc = max, 0v v in v cc -4 +4 a2 output leakage current i lo output(s) disabled, v out = v ss to v ccq -2 +2 a output high voltage v oh i oh = -1.0ma 2.0 --- v 1 output low voltage v ol i ol = 1.0ma --- 0.4 v 1 supply voltage v cc 2.375 2.625 v 1 i/o power supply v ccq 2.375 2.625 v 1 notes: 1) all voltages referenced to v ss (gnd) 2) zz pin has an internal pull-up and input leakage = 20 a. dc characteristics (-55c t a + 125c) bga capacitance (t a = + 25c, f = 1mhz) note: 1) this parameter is not tested but guaranteed by design. description symbol max units notes control input capacitance (lbo#, zz) c ic 16 pf 1 control input capacitance c i 8pf1 input/output capacitance (dq) c o 10 pf 1 address capacitance c a 16 pf 1 clock capacitance c ck 6pf1 note: i dd is speci ed with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. thermal resistance parameter symbol max unit thermal resistance: die junction to ambient ja 28.7 c/w thermal resistance: die junction to ball jb 16.0 c/w thermal resistance: die junction to case jc 7.1 c/w note: refer to application note ?pbga thermal resistance corrleation? for further information regarding wedc?s thermal modeling.
wedpz512k72s-xbx 7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 ac characteristics (-55c t a +125c) notes: 1) all address inputs must meet the speci ed setup and hold times for all rising clock (clk) edges when adv is sampled low and cs#x is sampled valid. all other synchronous inputs must meet the speci ed setup and hold times whenever this device is chip selected. 2) chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3) a write cycle is de ned by we# low having been registered into the device at adv low. a read cycle is de ned by we# high with adv low. both cases must meet setup and hold times. output load (a) output load (b) (for t lzc , t lzoe , t hzoe , and t hzc ) dout zo=50 rl=50 vl=1.25 v 50pf* dout 15 38 5p f * + 2 . 5v 1 667 *including scope and jig capacitance ac test conditions parameter value input pulse level 0 to 2.5v input rise and fall time 1.0v/ns input and output timing reference levels 1.25v output load see output load (a & b) parameter symbol 150mhz 133mhz 100mhz units min max min max min max clock time t cyc 6.7 7.5 10.0 ns clock access time t cd -- 3.8 -- 4.2 -- 5.0 ns output enable to data valid t oe -- 3.8 -- 4.2 -- 5.0 ns clock high to output low-z t lzc 1.5 -- 1.5 -- 1.5 -- ns output hold from clock high t oh 1.5 -- 1.5 -- 1.5 -- ns output enable low to output low-z t lzoe 0.0 -- 0.0 -- 0.0 -- ns output enable high to output high-z t hzoe -- 3.0 -- 3.5 -- 3.5 ns clock high to output high-z t hzc -- 3.0 -- 3.5 -- 3.5 ns clock high pulse width t ch 2.5 -- 2.5 -- 3.0 -- ns clock low pulse width t cl 2.5 -- 2.5 -- 3.0 -- ns address setup to clock high t as 1.5 -- 1.5 -- 1.5 -- ns cke setup to clock high t ces 1.5 -- 1.5 -- 1.5 -- ns data setup to clock high t ds 1.5 -- 1.5 -- 1.5 -- ns write setup to clock high t ws 1.5 -- 1.5 -- 1.5 -- ns address advance to clock high t advs 1.5 1.5 1.5 ns chip select setup to clock high t css 1.5 1.5 1.5 ns address hold to clock high t ah 0.5 -- 0.5 -- 0.5 -- ns cke hold to clock high t ceh 0.5 -- 0.5 -- 0.5 -- ns data hold to clock high t dh 0.5 -- 0.5 -- 0.5 -- ns write hold to clock high t wh 0.5 -- 0.5 -- 0.5 -- ns address advance to clock high t advh 0.5 -- 0.5 -- 0.5 -- ns chip select hold to clock high t csh 0.5 -- 0.5 --- 0.5 -- ns
wedpz512k72s-xbx 8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to isb 2z . the duration of snooze mode is dictated by the length of time z is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. snooze mode description conditions symbol min max units current during snooze mode zz v ih isb 2z 20 ma zz active to input ignored t zz 2 cycle zz inactive to input sampled t rzz 2 cycle zz active to snooze current t zzi 2 cycle zz inactive to exit snooze current t rzzi ons snooze mode snooze mode timing diagram zz i supply clock a ll inputs (exce pt zz ) o utput (q) t zz t zz i t rzz t rzz i high- z d eselect o r r ea d only i isb 2z d on't ca r e d eselec t o r r ead only n o rmal o p era t i o n cycle when zz becomes a logic high, isb2z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed.
wedpz512k72s-xbx 9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 timing waveform of read cycle clk x cke x # cs x # address write# adv x oe# data out t ch t cl t ces t ceh t as t ah a1 a2 a3 t ws t wh t css t csh t oe t hzoe t lzoe t cd t oh t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t advh notes: write# = l means wex# = l, and bwx# = l csx# refers to the combination of cs1 0 #, cs2 0 and cs2 0 #, or cs1 1 #, cs2 1 and cs2 1 #.
wedpz512k72s-xbx 10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 timing waveform of write cycle t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 t ds t dh don?t care undefined t cyc a1 d3-4 t ces t ceh q0-4 t hzoe q0-3 clk x cke x # cs x # address write# adv x oe# data out data in notes: write# = l means wex# = l, and bwx# = l csx# refers to the combination of cs1 0 #, cs2 0 and cs2 0 #, or cs1 1 #, cs2 1 and cs2 1 #.
wedpz512k72s-xbx 11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 t ch t cl t ds t dh a2 a4 a5 d2 t oe t lzoe q1 don?t care undefined t cyc t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 a9 a8 clk x cke x # cs x # address write# adv x oe# data in data out notes: write# = l means wex# = l, and bwx# = l csx# refers to the combination of cs1 0 #, cs2 0 and cs2 0 #, or cs1 1 #, cs2 1 and cs2 1 #. timing waveform of single read/write
wedpz512k72s-xbx 12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 timing waveform of cke operation t ch t cl a1 a2 a3 a4 a5 t ces t ceh don t care undefined t cyc t ds t dh d2 q4 q1 t cd t lzc t hzc q3 a6 clk x cke x # cs x # address write# adv x oe# data in data out notes: write# = l means wex# = l, and bwx# = l csx# refers to the combination of cs1 0 #, cs2 0 and cs2 0 #, or cs1 1 #, cs2 1 and cs2 1 #.
wedpz512k72s-xbx 13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 timing waveform of ce operation t ch t cl a1 a2 a3 a4 a5 t cyc d5 q4 don?t care undefined t ces t ceh q1 q2 t oe t lzoe d3 t cd t lzc t hzc t dh t ds clk x cke x # cs x # address write# adv x oe# data in data out notes: write# = l means wex# = l, and bwx# = l csx# refers to the combination of cs1 0 #, cs2 0 and cs2 0 #, or cs1 1 #, cs2 1 and cs2 1 #.
wedpz512k72s-xbx 14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 0.61 (0.024) nom 1.27 (0.050) nom a b c d e f g h j k l m n p r t u 20.32 (0.800) nom 23.1 (0.909) max 17.1 (0.673) max 10.16 (0.400) nom 1.27 (0.050) nom 2.03 (0.080) max bottom view ? 0.762 (0.030) nom 9 8 7 6 5 4 3 2 1 device grade: m = military -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package: b = 152 plastic ball grid array (pbga) frequency (mhz) 100 = 100mhz 133 = 133mhz 150 = 150mhz 2.5v voltage configuration, 512k x 72 ssram zbl plastic white electronic designs corp. all linear dimensions are in millimeters and parenthetically in inches wed p z 512k 72 s - xxx b x ordering information package dimension: 152 bump pbga
wedpz512k72s-xbx 15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci cations without notice. november 2003 rev. 6 document title 512k x 72 synchronous sram ? nbl revision history rev # history release date status rev 0 initial release february 2001 advanced rev 1 changes (pg. 1, 5, 6, 13) 1.1 block diagram: change dq d to dq pd , font consistency 1.2 electrical characteristics note 2: change reference to ma instead of ma. 1.3 dc characteristics: adjust location of units & notes for i sb 2. 1.4 ac characteristics: change temperature range to (-55c t a +125c) 1.5 package dimension: adjust length line to end of package 1.6 block diagram: adjust look for consistency 1.7 dc characteristics: isb2 condition should read all inputs v il or v ih instead of > v ih 1.8 figure 2: inputs transition should not be shown fully connected. 1.9 figure 6: unknown text deleted from timing diagram 1.10 package dimension: ball diameter arrow corrected to point to ball. april 2001 advanced rev 2 change (pg. 1) 1.1 change status from advanced to preliminary november 2001 preliminary rev 3 changes (pg. 1, 2) 1.1 block diagram: address lines should be a0-18 1.2 pin con guration: add note *pin f8 reserved for a19 upgrade to 1mx72. november 2001 preliminary rev 4 changes (pg. 1, 5) 1.1 bga capacitance: remove references to temperature in individual conditions 1.2 change ci from 10pf to 8pf 1.3 change ca from 20pf to 16pf 1.4 change cck from 7pf to 6pf 1.5 add control input capacitance (cic) 16pf november 2002 preliminary rev 5 changes (pg. 5) 1.1 add thermal resistance table 1.2 update current values 1.3 update package mechanical drawing may 2003 preliminary rev 6 changes (pg. 1, 13, 14, 15) 1.1 change mechanical drawing to new style november 2003 preliminary

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